TITLE: ASSOCIATE PRINCIPAL ASIC DESIGN ENGINEER
REPORTS TO: HW DIRECTOR
SALARY: UP TO 85K
LOCATION: IRVINE, CA
RELOCATION: MAYBE, H1-B: YES

COMPANY DESCRIPTION:

The company is committed to being an innovative technology leader in storage networking technologies. The company leverages its core competency in designs of massive parallel processing, ASIC, storage and networking to deliver a line of robust, next generation IP Storage products. This Company provides ultra fast performance, high availability network storage solutions for enterprise level SAN and NAS storage networking applications. The company’s IP Storage products deliver very reliable, available and scalable capabilities at affordable prices. The company focuses its highly available solutions on server and storage OEM customers enabling them to deliver cutting-edge, value-added storage networking features such as link aggregation, failover, QoS, volume virtualization, and other differentiating next-generation iSCSI enhancements.

POSITION SUMMARY:

The candidate will participate in high speed, multi-million gate ASIC verification and design environment development for IP-SAN products in a start-up environment.

As an Associate Principal ASIC Engineer, the responsibilities include design verification, design environment setup and scripting, with some HDL coding, and lab bring-up and debug through volume production.

POSITION REQUIREMENTS:

• 3+ years of experience in ASIC design environments
• Candidate should be very familiar with industry standard HDL's (Verilog) and CAD tools (Synopsys Design Compiler, Primetime, etc)
• Programming skills in C and Perl
• Candidate must possess good communication skills and the ability to work well in a team
• Familiarity with Xilinx design methodologies and fluency in C++ and/or SystemC

   

EDUCATION:

BSEE or equivalent required. MSEE strongly preferred

 

TITLE: ASIC VERIFICATION ENGINEER
REPORT TO: DIRECTOR ASIC VERIFICATION
SALARY: UP TO 120K
LOCATION: IRVINE, CA
RELO: YES, H1-B: MAYBE

COMPANY DESCRIPTION:

The company is committed to being an innovative technology leader in storage networking technologies. The company leverages its core competency in designs of massive parallel processing, ASIC, storage and networking to deliver a line of robust, next generation IP Storage products. This Company provides ultra fast performance, high availability network storage solutions for enterprise level SAN and NAS storage networking applications. The company’s IP Storage products deliver very reliable, available and scalable capabilities at affordable prices. The company focuses its highly available solutions on server and storage OEM customers enabling them to deliver cutting-edge, value-added storage networking features such as link aggregation, failover, QoS, volume virtualization, and other differentiating next-generation iSCSI enhancements.

POSITION SUMMARY:

The successful candidate will be experienced in testing for standards compliance, development of test plans, functional modeling and performance analysis. Candidate must be familiar with ASIC design, simulation/verification techniques, design of RTL, test benches and functional models.

POSITION REQUIREMENTS:

• 6 + years of solid ASIC verification experience
• Thorough understanding of ASIC verification concepts and practices
• Fluency in Verilog and C++ and/or System C
• Background in networking, PowerPC processors and experience in hardware/software integration
• RTL design experience
• Experience working with one or more of the following technologies: RAID, PCI, PCIX, PCIe, DDR SDRAM, PPC, SAS, SATA
• Experience working in a lab debug environment
• Xilinx FPGA design, debug, and test
• Synplicity and Synopsys experience
• Must have good communication skills and the ability and desire to work as a team

   

EDUCATION:

BSEE plus MSEE preferred

 

TITLE: SENIOR TECHNICIAN
SALARY: 52-60k
REPORTS TO: VP HARDWARE
LOCATION: San Clemente CA
NO RELOCATION/NO H1-B

COMPANY DESCRIPTION:This is a development stage medical device company creating the next generation of implantable electronic device utilizing state-of-the-art technologies with the current target of the development of a family of devices that will afford patient treatment that has been, until now, unattainable with the current therapeutic modalities and technologies.

POSITION SUMMARY:The Senior Technician supports the development of the ICD

• Build, debug, and test prototype circuits from requirements
• Document all test fixtures from schematic entry to prototype verification
• Help support and maintain an efficient electronic laboratory
• This individual will act as a significant resource to the Design Engineers throughout all phases of product development
• Comply with all COMPANY approved design standards
• Comply with all design related standards as developed by external regulatory groups
• Comply with department and corporate quality initiatives
  

POSITION REQUIREMENTS:* Minimum 5 years experience as Electronics Test technician in an R&D or Engineering lab

• Must be proficient in prototyping/testing/debugging complex analog and digital circuitry
• Experience with FPGA and low-current or high-voltage components is desirable
• Supervisory experience in an electronics test lab is strongly desired
• Labview experience is required
• Ability to self-start and complete tasks with minimum supervision
• Excellent documentation skills
• Desire to work in a fast-paced start-up environmentMEDICAL DEVICE EXPERIENCED PREFERRED, NOT REQUIRED
  

EDUCATION: * An AA degree or equivalent in a technical discipline, Electronics or Electrical Engineering preferred