Position: RTL Verification Engineer (Contract)
Location: Santa Clara, CA

Perform pre-silicon validation of higher levels of hierarchy of a new GPU IP.

Your responsibilities will include:

  • Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers
  • Review test plans of memory sub system (including L1c, l2c, acem); modify if necessary
  • Write the tests outlined by test plan
  • Enhance testbench if necessary, e.g. add coverage assertions
  • Leverage unit level verification infrastructure
  • Debug test failures, fix test or testbench if necessary
  • Report RTL failures to RTL designers
  • Enhance test benches and tests to achieve coverage goals

Successful candidates for this position will have:

  • Experienced with verification methodology such as UVM (preferred)
  • Experience verifying memory subsystem components like caches and/or SOC (e.g. CPU, GPU, DSP, Video Processor)
  • Understanding of micro-architecture and logic design fundamentals, e.g. caches, coherency, memory translation
  • Composed functional coverage assertions, preferably using system Verilog
  • BSEE, or higher degree
  • At least 5 years of experience in a design verification role
  • Proficient in System Verilog
  • C++, Python/Perl skills are also desirable
  • Good verbal and written communication skills

If you think you have the qualifications and the experience, please send your resume to tanya@conneticsusa.com